PCIe-Based SD 7.0 Spec Closing In, Set to Be Announced This Month


PCIe-Based SD 7.0 Spec Closing In, Set to Be Announced This Month

By Anton Shilov

The SD Association plans to formally announce its Secure Digital 7.0 specification later this month. The new spec will define usage of a PCIe protocol for SD cards and will therefore significantly increase performance compared to existing cards that use the UHS-I or UHS-II buses.

Earlier this year Western Digital demonstrated a prototype SD card featuring a PCIe 3.0 x1 interface, whereas the SD Association announced plans to standardize usage of PCI Express on SD cards. As it turns out, SDA is accelerating its PCIe with SD effort and will formally announce publication of the spec at this year’s MWC Shanghai that takes place on June 26 – June 28.

Details regarding the spec are unknown at this point. Meanwhile Western Digital’s implementation demonstrated at MWC used the existing UHS-II/III pins to construct a PCIe 3.0 x1 interface with the host and probably standard PCIe voltage with a converter. The card offered 880 MB/s sequential read speeds as well as up to 430 MB/s sequential write speeds, according to the CrystalDiskMark benchmark, which is considerably higher compared to cards featuring the UHS-II bus (up to 312 MB/s full duplex), and about 40% higher when compared to cards featuring the UHS-III bus (up to 624 MB/s full duplex).

Usage of a PCIe protocol will solve a number of performance-related challenges for the SD standard in general but will create new ones too. Firstly, it will enable SD cards to increase their performance and will ensure a steady and straightforward path for performance upgrades in the future. Secondly, it will simplify implementation of high-performance SD card readers on PCs and similar devices that run chips that already support PCIe. In theory, PCIe might enable the SD technology to go beyond cards and into highly-integrated storage modules (like eMMC, UFS, etc.) for various applications. However, there will be challenges too: PCIe is not exactly power efficient (this might change with PCIe 4.0 though), PCIe is not supported by most smartphone/camera SoCs because of power and some other factors. Moreover, the SDA wants PCIe-based SD cards (and probably hosts) to be backward compatible, which means additional complications.

In any case, the aforementioned are just theoretical effects a PCIe interface could bring to the SD world. The formal announcement is just weeks away, so we will learn all the information shortly from now.

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