Intel: EUV-Enabled 7nm Process Tech is on Track


Intel: EUV-Enabled 7nm Process Tech is on Track

By Anton Shilov

Originally planned to enter mass production in the second half of 2016, Intel’s 10nm process technology is still barely used by the company today. Currently the process is used to produce just a handful of CPUs, ahead of an expected ramp to high-volume manufacturing (HVM) only later in 2019. Without a doubt, Intel suffered delays on its 10nm process by several years, significantly impacting the company’s product lineup and its business.

Now, as it turns out, Intel’s 10nm may be a short-living node as the company’s 7nm tech is on-track for introduction in accordance with its original schedule.

For a number of times Intel said that it set too aggressive scaling/transistor density targets for its 10nm fabrication process, which is why its development ran into problems. Intel’s 10nm manufacturing tech relies exclusively on deep ultraviolet lithography (DUVL) with lasers operating on a 193 nm wavelength. To enable the fine feature sizes that Intel set out to achieve on 10nm, the process had to make heavy usage of mutli-patterning. According to Intel, a problem of the process was precisely its heavy usage of multipatterning (quad-patterning to be more exact).

By contrast, Intel’s 7nm production tech will use extreme ultraviolet lithography (EUVL) with laser wavelength of 13.5 nm for select layers, reducing use of multipatterning for certain metal layers and therefore simplifying production and shortening cycle times. As it appears, the 7nm fabrication process had been in development separately from the 10nm tech and by a different team. As a result, its development is well underway and is projected to enter HVM in accordance with Intel’s unannounced roadmap, the company says.

Murthy Renduchintala, chief engineering officer and president of technology, systems architecture and client group at Intel is quoted to have said at the Nasdaq’s 39th Investor Conference:

“7nm for us is a separate team and largely a separate effort,”

“We are quite pleased with our progress on 7nm. In fact, very pleased with our progress on 7m. I think that we have taken a lot of lessons out of the 10nm experience as we defined that and defined a different optimization point between transistor density, power and performance and schedule predictability. […] So, we are very, very focused on getting 7nm out according to our original internal plans.”

The Intel exec reaffirmed the company plans to start HVM production of client CPUs using its 10nm process technology in 2019, with datacenter products following on a bit later. That said, Intel is clearly not skipping any of its already announced 10nm products, but implies that its 7nm products may hit the market earlier than we might expect today (i.e., four years after the 10nm).

“One thing I will say is that as you look at 7nm, for us this is really now a point in time where we will get EUV back into the manufacturing matrix, and therefore, I think, that will give us a degree of back to the traditional Moore’s Law cadence that we were really talking about,”

“[With 7nm] we are going back to more like a 2X scaling factor […] and then really moving forward with that goal.”

Intel has never disclosed characteristics of its 7nm fabrication tech, but a major reduction of multi-patterning usage as well as a more traditional 2X scaling goal vs. 10nm indicates a more extensive usage of EUVL.

According to ASML, one EUV layer requires one EUV step-and-scan system for every ~45,000 wafer starts per month. Therefore, if Intel plans to use EUVL extensively for 10 to 20 layers, it will require approximately 20 to 40 EUVL scanners for a fab with a 100,000 wafer starts per month capacity. Considering that Intel is not the only company with plans to use EUVL in the 2020s, getting the number of EUVL scanners it might need for HVM at multiple fabs may be a challenge.

Meanwhile, so far Intel has announced plans for only one 7nm fab: the Fab 42 in Arizona. In addition, the company is going to have some 7nm-capable capacity at its D1 facility used for development and trials (among other things).

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Sources: Intel, SeekingAlpha

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